This was a array processor which was attached to ICL mainframes and could also be accessed as ordinary memory. It consisted of 64x64 single bit processors with 4k bits of memory each plus an overall master control unit which had its own 64 bit registers.
Click on any of these to get a larger version:
DAP wasn't much of a success for ICL, it really had no feel for the technical as opposed to the commercial market. Our first customer nearly was BACS using some of them to do their bank clearing! That's why it was later farmed off to form separate company Active Memory Technology (AMT). Cambridge Parallel Processing soon thereafter took it over. I've got a copy here of the technical overview of the AMT Gamma series which had much improved processing and I/O capability. The document came from the www.cppus.com site stored on the very excellent Internet Archive Wayback machine.
Gamma IIPlus Technical Overview
See Wiki on International Computers Ltd for more about ICL, it was later incorporated into Fujitsu.
I did various bits of work on the DAP including devising and implementing a Block I/O system for which one could have either physical blocks or logical blocks, so I was able to get the documentation to talk about 'BIO logical transfers'!. Unfortunately they noticed and changed it to BTS (Block Transfer System).
Examples of DAP APAL (Array Processor Assembly Language) with a 'description' of each function above in DAP Fortran:
!
!-------------------------------------------------
! LOGICAL MATRIX FUNCTION FRSTV (LMATRIX)
! LOGICAL LMATRIX(,)
! FRSTX = .FALSE.
! FRSTX(ROWN(LMATRIX),) = .TRUE.
! RETURN
!
ENTRY FRSTR DAP
QT
CQ
QS_AS 0(M2)
QVCQ S P 16
QPCQ
AMQ
QA
SQ 0(M1)
EXIT
!
!-------------------------------------------------
! LOGICAL VECTOR FUNCTION FRSTV ( LVECTOR )
! LOGICAL LVECTOR()
! FRSTV = FRST ( LVECTOR )
! RETURN
!
ENTRY FRSTV DAP
RX M3 0(M2)
RAR M4 'LOWER_TRI
AR M3
AMS 0(M4)
RANO M2
RRN M3 M2
SHR M4 M3 1
NEQ M3 M4
XR M3 0(M1)
EXIT